Registered buffers are used in a number of conventional circuits. Registered buffers as for example used in Double Data Rate 3 (DDR3) memory systems buffer incoming data (control data and address information) and output the received data with a refreshed waveform. These registered buffers include a phase locked loop (PLL) and a phase interpolator for phase aligning the output clock with respect to the refreshed data.
Referring to FIG. 1, a DDR3 system 100 is shown. Here, a memory controller 102 provides address information and clock signals to dual inline memory modules (DIMMs) 104-1 to 104-n. DIMM 104-1 is shown in more detail. DIMM 104-1 includes a registered buffer 106 receiving address information at data input Dn and clock signals at clock input CLK. The registered buffer 106 refreshes and phase aligns the data and transmit it to several sychronous DRAM (SDRAM) modules 108-1 to 108-m through data output Qn using clock signal QCLK. Data from and to the SDRAM modules 108-1 to 108-m is transferred through a data bus coupled between data pins Data-1 to Data-m, strobe signals Strobe-1 to Strobe-m, and SDRAM modules 108-1 to 108-2. Registered buffer 106 uses a feedback loop between pins FBOUT and FBIN for its internal PLL in order to adapt, for example to different load conditions and ambient conditions such as temperature. The data signals Dn (and Qn) include the memory system addresses and command/control signals from the memory controller 102. Generally, registered buffer 106 serves to improve data waveforms and phase alignment of data and clock signals and to reduce clock jitter. Registered buffer 106 should provide a good data eye opening and small propagation delay of the data from the device inputs to the device outputs. A sufficient data eye opening at the data output pins is required in order to generally ensure a safe and successful data transfer to the receiving DRAM devices (such as SDRAM modules 108-1 to 108-m). A small propagation delay supports an overall low system latency, i.e. a short time for writing data into and reading data form the SDRAM modules 108-1 to 108-m. 
Turning to FIG. 2, a simplified block diagram of registered buffer 106 with a PLL clock driver can be seen. The registered buffer 106 shown in FIG. 2 generally comprises input stages (input buffers B1 to B3) for input data signals Dn, input clock signal CK and feedback input clock signal FBIN, output stages (output buffers B4 to B7) for output data signals Qn, output clock signals Yn and feedback output clock signal FBOUT. There is also a data register that generally comprises several flip-flops FF1, a data reference path with a dummy output stage B5, a PLL 110, a phase aligning state machine PASM, a phase interpolator PINT, a delay element DLY, and a phase comparator PCOMP. Although there is only one data path PQn shown in FIG. 2, there are usually numerous similar data paths for a plurality of data signals Dn (IDn) of a bus. The PLL 110 receives the input clock CK as a reference clock ICK and the feedback input clock FBIN as PLL 110 feedback clock IFBIN. The PLL 110 generates the feedback output signal PFBOUT which is then output from as signal FBOUT after being buffered in output buffer B7. The PLL 110 is coupled to phase interpolator PINT and feeds a set of phase shifted output clock signals CK1 to CKn to phase interpolator PINT. Phase interpolator PINT generates output clock signal PYn, which is buffered in output stage B6 and output as the output clock Yn. The clock frequency FCK of all PLL output clock signals CK1 to CKn and the feedback output clock FBOUT is equal to the clock frequency of the input clock signal CLK. A clock period TCK refers to a clock frequency FCK.
The purpose of the PLL 110 is to generally provide output clock signals Yn with reduced input clock jitter, which are phase aligned (i.e. phase shifted) with respect to the input clock signal CLK. Data transfer from the data inputs Dn to the data outputs Qn is triggered by the input reference clock CK. Therefore, the propagation delay TPD (CK to Qn) from the clock input pin CK to the data output Qn consists of the propagation delay through the clock input stage B2, the data flip-flop FF1 and the data output stage B4. The propagation delay TPD (CK to Qn) depends on the electrical characteristics of the transistor devices of the dies or wavers (weak, nominal or strong process material). The phase relationship of the output clock Yn is individually trained for each registered buffer device during the power up procedure. During this training procedure, the phase of the output clock Yn is shifted such that a maximum output data eye opening is achieved. A maximum output data eye opening means that the rising edge of the output clock Yn is in the middle of an output data high or low pulse assuming that the data signal Dn/Qn has a signal frequency which is half the input clock frequency FCK.
Tuning to FIG. 3, the propagation delay for clocks CK (and CKN) data signals Dn and Qn, and output clock signals Yn and YnN, where the capital “N” indicates the inverted signal. Differential data and clock signals are also used. The propagation delay form clock edge of clock signal CK to changing data Qn is indicated as TPD (CK→Qn). The phase of clock signal PYn in the output clock path is compared with the phase of the data reference signal PRQn in the data reference path. The data signal PRQn is generated by a data reference path flip-flop FF2 toggling with the input clock frequency FCK. The frequency of reference data signal PRQn is half the frequency FCK of input clock signal CK. Clock signal PYn is also divided by two in order to receive the same clock frequency as PRQn. In order to compensate the time delay of this division by two (i.e., the delay of the respective circuitry), it is necessary to insert an equivalent time delay element DLY into the reference path for PRQn. The delayed signal PRQn and the divided signal PYn are fed to phase comparator PCOMP. The output of phase comparator PCOM is coupled to phase aligner state machine PASM, which determines whether the PYn phase needs to be shifted a certain amount forward or backward compared to the PRQn signal. In order to adapt the phase, a phase aligning control word PACW is generated in phase aligning state machine PASM and passed to phase interpolator PINT. Phase controller PACW selects the desired PLL phase for clock signal PYn. Signal PYn is buffered in buffer B6 and is output as the output clock signal Yn. The phase aligning state machine PASM not only monitors the phase relationship between reference data signals PRQn and clock signal PYn, but also surveys the phase relationship between clock signal ICK and clock signal IFBIN (i.e., the phase relationship between the clock reference and the clock feedback inputs). Based on these comparison results, the phase aligning state machine PASM decides when the PLL 110 and the phase aligner phase alignment are locked and when the phase aligning training can be stopped. When the PLL and phase aligning are locked and the phase aligning training is completed, the phase aligning control word PACW remains fixed. The phase of the output clock Yn is then fixed. After having completed the PLL 110 power up and phase aligning training procedure, the registered buffer 106 returns to normal operation mode for a specific application. The phase of the output clock Yn is generally not be changed during normal operation as the memory controller 102 is trained with the fixed phase of Yn. The phase aligning training is only performed once during an initial power up procedure. It may also be performed in response to an external training trigger signal TPAT.
An important device parameter is TQsk. TQsk is the relationship between the output clock Yn and the output data Qn and can serve as an indicator for the quality of the data output eye. FIG. 4 shows waveforms illustrating the meaning of TQsk. TQsk describes the time (or phase) difference of the rising or falling edge of the output data signal Qn with respect to the falling edge of the output clock signal Yn. If the signal edges of Qn are very close to the falling edge of Yn, the corresponding rising edge of Yn is almost ideally centered in the middle of the output data signal Qn (e.g. high or low pulse). If the signal edge of Qn is outside the specified limits TQskmin or TQskmax, the rising edge of Yn is outside the desired ideal middle position in the output data pulse and Qn may not be decoded correctly in a DRAM receiving Qn.
A problem with prior art devices is that the initial training procedure for the clock phase alignment is performed at arbitrary conditions. If these conditions (for example, temperature and supply voltage level) vary for a specific clock frequency, the specified minimum or maximum values TQskmin, TQskmax for TQsk can be exceeded. This would require retraining of the registered buffer 106, which is not allowed since the memory controller 102 relies on the fixed phase of the output clock Yn during normal operation. Furthermore, it can be difficult to determine whether or not retraining is required. Transmission errors or total failure of the system can be the consequence.